During ESD, large currents can flow through an IC which can potentially cause damage. Damage can occur within the devices that conduct the current, as well as in devices that see a significant voltage drop due to the large current flow. To avoid damage due to an ESD event, clamps are added to the IC. These clamps may shunt the large ESD current without causing high voltage over sensitive nodes of the IC.
One concern with designing such ESD clamps is that they might shunt current during normal operating conditions, which may result in temporary loss of function, sometimes requiring human or other IC interaction to restore the normal operation. Further, if the clamps trigger in low conductive (shunt) mode during normal operation, the energy of the current through the clamp may be too high such that temporary or permanent damage can occur. An increased (supply) current during normal operation, often caused by faulty triggering of the ESD device, is called a latch up event, and might result in temporary loss of function, temporary damage, or permanent damage. EOS is most often caused by unwanted high voltages at IC pins.
A known way to overcome these issues is by creating ESD clamps with a high holding voltage. The holding voltage of the clamp is the lowest voltage at which the device can sustain its high conductive state. By increasing the holding voltage above the supply level, the ESD clamp is designed to release from latched state even if triggered during normal operation, such that the loss of function is at most temporary.
For some applications, such as automotive, a holding voltage may be much higher than the supply level, in order to avoid noise spikes causing temporary loss of function, or in order to allow off-chip ESD protection to shunt system-level ESD currents without triggering the on-chip ESD protection.
A further requirement for the ESD protection clamp may be to have a low standby or leakage current. For some applications, the amount of capacitance added to the pad must be minimized as well.
These concerns may be mostly problematic for high voltage ICs, wherein increasing the holding voltage typically comes at great silicon area cost. The creation of these ESD clamps for high voltage applications may typically take multiple silicon test runs to tune the ESD clamp device to have the desired holding and trigger voltage.
Yet another concern in high voltage technologies is the response time of the ESD clamp to an ESD event. The base transit times of bipolar devices in these technologies may be in the same order of magnitude or larger than the rise time of the ESD events. As such, the reaction of the clamp to an ESD event might be too late to effectively protect the IC.
No solution currently exists that combines the advantage of a tunable high holding voltage and appropriate trigger voltage within a reasonable silicon area, without the need for extensive process tuning or extensive, multiple test chip creation.
Therefore, there is a need in the industry for an improved ESD protection clamp, which combines the advantages of high and tunable holding voltage, low leakage, high and tunable trigger voltage, small silicon area for high current capability and fast and effective triggering without the need for multiple silicon runs to tune the important parameters of the clamp.
A holding voltage higher than the supply voltage may be desirable for ESD clamp devices to prevent latch up and false triggering due to events in the system. Such holding voltages can be reached by stacking a number of elements from a lower voltage domain in series. Since these elements are designed for a lower voltage domain, the stack might exhibit high leakage. In both cases, chip performance may be endangered by either oxide reliability or high leakage.
FIG. 1 shows a conventional ESD clamp. A gate-grounded N-type metal oxide semiconductor (ggNMOS) device is created, often using specific process adaptation techniques to achieve good ESD characteristics. Very often additional doping levels are needed specifically for ESD, increasing the cost of the process.
FIG. 2 shows another conventional ESD clamp. A high voltage (HV) silicon controller rectifier (SCR) is developed, wherein the ESD characteristics are tuned using layout and process techniques. The SCR may be triggered by some internal reverse junction breakdown.